1. Field of the Invention
The present invention generally relates to image forming apparatuses, such as printers, copiers, facsimiles, etc., and more particularly to image forming apparatuses capable of efficiently accessing a non-volatile memory, which stores maintenance and supervisory information related to the image forming apparatuses, and capable of obtaining a high performance while reducing load on a CPU.
2. Discussion of the Background
Recently, various high value-added functions are proposed to be equipped with image forming apparatuses such as digital copiers, etc., and are gradually being adopted therein. For example, usage career data, such as indicating a number of used sheets and so on, is stored in a non-volatile memory, and a parameter for controlling an image forming process is changed in accordance with the usage career data to thereby obtain a stable image over a long period of time. In addition, career data related to a problem such as a paper jam, a self-diagnosis error, etc., is also stored in the non-volatile memory, and maintenance is performed in accordance with the career data as appropriate. Further, data indicating a unique operational procedure is also stored in the non-volatile memory per a user or an objective job so that an operational condition can be set and customized. Thus, the above-described usage information is included, for example, in a digital copier as important information to improve usability when a maintenance is performed and the image forming apparatus is supervised. Accordingly, the usage information should not be subject to a problem such as a data crash.
For a non-volatile memory storing such usage career data, a NVRAM (Non-Volatile Random Access Memory) or an EEPROM (Electrically Erasable and Programmable Read Only Memory) is frequently employed. The NVRAM is generally more compact and cheaper than a magnetic memory such as a hard disc memory, and generally has an advantage that a backup use power supply is unnecessary when compared with a DRAM (Dynamic Random Access Memory) and an SRAM (Static Random Access Memory). The NVRAM includes a memory cell composed of a pair of cells of the SRAM and EEPROM and functions to store data of the SRAM into the EEPROM. The NVRAM recalls data of the EEPROM to the SRAM. In addition, depending upon a usage manner, the NVRAM does not have to consider a life of the EEPROM. However, a variety in NVRAM rarely exists and the NVRAM is sometimes costly when compared with an EEPROM.
In contrast, the EEPROM includes varieties and is relatively cheaper. However, a memory such as an EEPROM generally has a lifetime limited by a number of rewriting times (e.g. from a few thousand to a few hundred-thousand times). Thus, if rewriting in the EEPROM is performed every access to the CPU, an expected product life of an image forming apparatus may not coincide with the life of the EEPROM. As a result, an operation of the image forming apparatus is not assured.
In view of such an aspect, an accessing system is proposed. For example, a working area is formed in a section of a memory such as an SRAM, a DRAM, etc., and contents (data) in the EEPROM are copied to the working area when the electrical power is supplied to the image forming apparatus. Typical reference and update operations are performed with regard to the working area, and the contents of the EEPROM are periodically updated by the contents of the working area. In such a situation, a value obtained by dividing a lifetime (e.g. 5 to 10 years) of the digital copier with a number of times that an EEPROM can be accessed can be set as a number of times for updating the EEPROM.
FIG. 12 illustrates an exemplary control section that operates in accordance with the background accessing operation. A main control section 21 of a digital copier is controlled by a CPU 211, and includes a ROM 212, an operation memory 213, e.g. a working memory, a timer 214, and a non-volatile memory 215, respectively, connected to each other by a CPU bus. The CPU 211 of the main control section 21 performs a series of control operations in accordance with a control program stored in the ROM 212 after the electrical power is supplied (ON).
The operation memory 213 is utilized as a working area, and the non-volatile memory 215 is utilized to store a variety of important information to be preserved together with the above-described usage information. The timer 214 is provided to generate a timing signal for periodically updating the non-volatile memory 215.
FIG. 13 illustrates a background operation control flow for reading and writing data from and to a non-volatile memory in the system of FIG. 12. Referring to FIG. 13, the electrical power is initially supplied (step S61), and data of the non-volatile memory 215 is simultaneously copied to the operation memory 213 (step S62). Then, reference and update operations are performed (not shown in the flow) with regard to the operation memory 213 to change usage information stored therein in accordance with a change in usage information when an image forming apparatus is operated. However, the non-volatile memory 215 is not accessed. Subsequently, the timer 214 performs a timing and determines a preset writing cycle (step S63), and data of the operation memory 213 is copied to the non-volatile memory 215 every timeout (step S64). Then, the timer 214 is reset (step S65), and the flow is terminated.
Such a writing cycle of the timer 214 is generally optionally set. Thus, if the writing cycle is preferably set in view of a rewritable lifetime of the non-volatile memory 215, the lifetime can coincide with a product lifetime of the image forming apparatus.
FIG. 14 illustrates a usage condition of such a background system that updates information stored in the non-volatile memory at a cycle set by the timer. As shown in FIG. 14, an update duration of 10 milliseconds for updating the non-volatile memory 215 periodically occupies the CPU bus in a timeout cycle of 80 ms, and accordingly, performing a task A (50 ms) three times and a task B (30 ms) twice takes 240 ms, totally.
Like the control system of FIG. 12, when the operation memory 213 and the non-volatile memory (EEPROM) 215 are connected to the same CPU bus, the CPU bus is occupied by such an updating operation for the non-volatile memory 215 as illustrated in FIG. 14. Thus, if an amount of information to be transferred to the non-volatile memory 215 is small, there is almost no problem. However, based upon the recent tendency to desire high performance, an amount of the information to be preserved in the non-volatile memory 215 is increasing. As a result, updating the non-volatile memory 215 now takes a more significant period of time, and the result is that there is a probability of lowering a performance of the entire system of the image forming apparatus.